Applied Physics Letters 107, 123502 (2015)
Applied Physics Letter with co-authors from SK Hynix and UC Berkeley detailing the origins of the very large (88%) measured increase in conductance (gm) for Oxygen Inserted (MST®) nMOS devices.
IEEE Transactions Electron Devices, vol. 61, no. 9, pp 3345-3349, September 2014
Paper with co-authors from UC Berkeley describing the wide range of power and performance benefits of MST® to extend the industry scaling of low power bulk nMOS devices.
2014 IEEE Silicon Nanoelectronics Workshop
June 8, 2014
Paper with authors from UC Berkeley describing how MST® can enhance a new quasi-planar device, the SegFET, with performance that competes with the best 10nm generation devices for Systems-on-a-chip (SOC) applications.
Comparative Study of Uniform Versus Supersteep Retrograde MOSFET Channel Doping and Implications for 6T SRAM Yield
IEEE Transactions Electron Devices, vol. 60, no. 5, pp 1790-1793, May 2013
May 5, 2013
Joint paper with UC Berkeley simulating the improved yield and reduced minimum operating voltage of MST®-enabled 6-T SRAM cells with potentially up to 50% power savings.
2013 IEEE Silicon Nanoelectronics Workshop
June 9, 2013
Details the benefits of MST® for silicon and germanium p-type planar & FinFET devices over a wide range of technologies.
Simultaneous Carrier Transport Enhancement and Variability Reduction in Si MOSFETs by Insertion of Partial Monolayers of Oxygen
2012 IEEE Silicon Nanoelectronics Workshop
June 10-11, 2012
We demonstrate simultaneous nMOS and pMOS high-field mobility enhancement and variability reduction by inserting partial monolayers of oxygen during silicon epitaxy of the channel layer.
IEEE IEDM 2012
December 12, 2012
IEDM paper with UC Berkeley, introducing and calibrating the model for the MST® confinement effect using Synopsys Sentaurus platform simulation tools. Mobility (conductivity) enhancement for both nMOS and pMOS devices is demonstrated and predicted to be more effective than strain at the 14nm node.
Journal of Physics: Condensed Matter, Volume 24, Number 49
November 12, 2012
Paper analyzing the origins of tunneling of carriers in various superlattice systems and providing a theoretical background for the observed reduction in gate leakage in MST® devices. Gate leakage is one of the sources of power loss and scaling limitation in advanced CMOS technology.
IEEE International SOI Conference 2007
October 1-4, 2007
This joint experimental paper with authors from Texas Instruments and Sematech (ATDF) demonstrates the first MST® mobility enhancement and gate leakage reduction results for a MST-enhanced silicon-on-insulator (SOI) technology.