HKMG Devices Work Better With MST, Extending the CMOS Roadmap
By Robert Mears, Atomera Founder and CTO
Nearly five years ago, Atomera started working with Prof. Suman Datta’s group at Notre Dame to quantify the benefits MST® brings to high-k/metal-gate (HKMG) devices. Prof. Datta previously worked at Intel, and was awarded the Intel Achievement Award (the highest technical honor at Intel) for “developing the world’s first high-k/metal gate CMOS transistors with record-setting performance”.
The Atomera and Notre Dame team was rapidly able to demonstrate that MST technology does indeed improve the carrier mobility and reduce gate leakage, as had been seen in other technologies. That work was first published in the IEEE Device Research Conference (DRC 2018).
The key results, verified in MST silicon devices compared to control silicon, were a 24% higher linear current (Idlin) and an 18% higher saturation current (Idsat) for the same overdrive. (MST is referred to in our publications as oxygen insertion technology (OI) because of restrictions on use of trademarks). Significantly, a gate leakage reduction of 2.7x was also measured compared to control devices. Whereas the drive current improvements were in line with previous characterizations of MST on other devices, the gate leakage reduction was about twice as large as that seen for MST with regular silica and nitride-silica gate dielectrics.
These results prompted the team to make a more detailed characterization of the influence of MST on the formation of the HKMG stack. We have found that the MST oxygen layers, even when they are buried about 10nm below the gate dielectric itself, have a profound beneficial impact on the formation of the gate stack. The first publication of this data was made today in the Journal of Applied Physics, and is available for public download for the next 15 days. The link is:
https://doi.org/10.1063/5.0068002
First, detailed characterization of the gate leakage confirmed a 250mV higher barrier to Fowler Nordheim tunneling (1.74V compared to 1.49V) for MST. This is consistent with the previously observed gate leakage reduction, but overall, the gate leakage reduction is more pronounced for higher gate overdrive, rising from 50% reduction for 1V overdrive to 100% reduction for 2V overdrive.
Second, it was found that the stress-induced leakage current (SILC) is also reduced for MST. Samples were first subjected to a constant current density of 0.1A/cm2. The MST samples retained a higher barrier after stress.
This data suggests that HKMG stacks grown on MST will be more robust to electrical stress. The Atomera & Notre Dame teams have projected that MST will improve bias temperature stability (BTI), which is a known weakness for HKMG, although further characterization will be needed.
To probe more deeply into the origins of these improvements, a variety of spectroscopic and other metrology approaches were used to characterize the individual gate stack layers.
It has been known for many years that when the high-k material hafnium dioxide is grown on silicon, an interfacial layer (IL) of silica forms between the silicon and the hafnium oxide. One theory for this phenomenon is that that oxygen is “scavenged” from elsewhere to form the IL, until there is a balancing dipole formed at the silicon interface. Surprisingly, it was found that all the interfaces in the gate stack were more abrupt in the samples grown on MST compared to the control, with up to 30% steeper transitions (as measured in nm/decade, a typical metric used for comparing interfaces) even when the MST oxygen layers are buried about 10nm below the gate dielectric. Since silica has a much lower dielectric constant, the IL formation ultimately limits the scaling potential of HKMG, and is also associated with some of the deficiencies in its performance. MST has the prospect of enabling better scaling of HKMG devices.
Even more intriguingly, the analysis revealed that the MST devices have lower flat-band shift, which in conjunction with the other data suggests that the interfacial dipole is reduced for MST. Thus the insertion of MST can be used to tune the HKMG metal work function. The device benefit is that MST devices can have a lower threshold voltage for the same grown hafnium oxide thickness.
In gate-all-around (GAA) structures under development for the 2/3nm node, the ability of MST to engineer lower Vt can be used to reduce deposited layer dimensions and hence improve the stacking density.
In summary, MST offers significant scaling benefits for advanced node development. As the paper concludes:
“OI-Si promises significant performance boost for the end-of-roadmap planar CMOS products with HKMG stack, due to its unique carrier mobility improvement [35], gate leakage reduction [35], and reduction of random dopant fluctuations [36]. In addition, the newly observed interfacial charge dipole reduction opens an opportunity for OI-Si as the metal work function tuning layer in HKMG-based semiconductor products, which is particularly important for next generation non-planar CMOS.”