Technology

Patents

The Core of Atomera’s IP Portfolio

Atomera is a technology licensing company, so our patents are a fundamental building block of our business.  We partner with customers through licensing arrangements, providing them access to our patents and proprietary know-how to enable integration of our MST® technology into their semiconductor manufacturing processes.

Below is a list of our issued US patents.  We also hold foreign counterparts in all the major jurisdictions where our customers, prospects and partners do business, and have a number of patents pending.

# of issued and pending patents worldwide, as of September 30, 2021

[#7071119] - A Method for Making a Semiconductor Device Including Band-engineered Superlattice Having 3/1-5/1 Germanium Layer Structure
PATENT NUMBER: 7071119 
PUBLICATION DATE: 4/28/2005

Abstract:

A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. The device may also include regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Moreover, the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Accordingly, the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise be present.

See Patent

[#10355151] - CMOS Image Sensor Including Photodiodes With Overlying Superlattices To Reduce Crosstalk
PATENT NUMBER: 10355151 
PUBLICATION DATE: 6/20/2019

Abstract:

A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a plurality of laterally adjacent photodiodes formed in the substrate. Each photodiode may include a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the second conductivity type, and a second well within the retrograde well having the first conductivity type. Each photodiode may further include first and second superlattices respectively overlying each of the first and second wells. Each of the first and second superlattices may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

See Patent

[#10529757] - CMOS Image Sensor Including Pixels With Read Circuitry Having A Superlattice
PATENT NUMBER: 10529757 
PUBLICATION DATE: 6/20/2019

Abstract:

A CMOS image sensor may include an active pixel sensor array including pixels, each including a photodiode and read circuitry coupled to the photodiode and including transistors defining a 4T cell arrangement. At least one of the transistors may include a first semiconductor layer and a superlattice on the first semiconductor layer including a plurality of stacked groups of layers, with each group including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The transistor(s) may also include a second semiconductor layer on the superlattice, spaced apart source and drain regions in the second semiconductor layer defining a channel therebetween, and a gate comprising a gate insulating layer on the second semiconductor layer and a gate electrode on the gate insulating layer.

See Patent

[#10367028] - CMOS Image Sensor Including Stacked Semiconductor Chips And Image Processing Circuitry Including A Superlattice
PATENT NUMBER: 10367028 
PUBLICATION DATE: 6/20/2019

Abstract:

A CMOS image sensor may include a first semiconductor chip including image sensor pixels and readout circuitry electrically connected thereto, and a second semiconductor chip coupled to the first chip in a stack and including image processing circuitry electrically connected to the readout circuitry. The processing circuitry may include a plurality of transistors each including spaced apart source and drain regions and a superlattice channel extending between the source and drain regions. The superlattice channel may include a plurality of stacked groups of layers, each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. Each transistor may further include a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.

See Patent

[#10615209] - CMOS Image Sensor Including Stacked Semiconductor Chips And Readout Circuitry Including A Superlattice
PATENT NUMBER: 10615209
PUBLICATION DATE: 6/20/2019

Abstract:

A CMOS image sensor may include a first semiconductor chip including an array of image sensor pixels and readout circuitry electrically connected thereto, and a second semiconductor chip coupled to the first semiconductor chip in a stack and including image processing circuitry electrically connected to the readout circuitry. The readout circuitry may include a plurality of transistors each including spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate including a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.

See Patent

[#10276625] - CMOS Image Sensor Including Superlattice To Enhance Infrared Light Absorption
PATENT NUMBER: 10276625
PUBLICATION DATE: n/a

Abstract:

A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a plurality of laterally adjacent infrared (IR) photodiode structures on the substrate. Each IR photodiode structure may include a superlattice on the semiconductor substrate including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Further, the superlattice may have the first conductivity type. The CMOS image sensor may further include a semiconductor layer on the superlattice, a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type.

See Patent

[#10304881] - CMOS Image Sensor With Buried Superlattice Layer To Reduce Crosstalk
PATENT NUMBER: 10304881 
PUBLICATION DATE: 6/20/2019

Abstract:

A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a superlattice on the semiconductor substrate including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. The image sensor may further include a plurality of laterally adjacent photodiodes on the superlattice. Each photodiode may include a semiconductor layer on the superlattice and having a first conductivity type dopant and with a lower dopant concentration than the semiconductor substrate, a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type.

See Patent

[#7123792] - Configurable Aperiodic Grating Device
PATENT NUMBER: 7123792 
PUBLICATION DATE: n/a

Abstract:

The invention relates to the field of grating structures. The invention provides a longitudinal grating having an aperiodic structure, wherein the grating has a selected response characteristic and any repeated unit cell in the structure is significantly longer than a characteristic length associated with the selected response characteristic.

See Patent

[#10109342] - Dram Architecture to Reduce Row Activation Circuitry Power And Peripheral Leakage
PATENT NUMBER: 10109342
PUBLICATION DATE: 11/16/2017

Abstract:

A semiconductor device may include a plurality of memory cells, and at least one peripheral circuit coupled to the plurality of memory cells and comprising a superlattice. The superlattice may include a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during a first operating mode, and a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a second operating mode.

See Patent

[#10367064] - DRAM With Recessed Channel Array Transistor (RCAT) Including A Superlattice And Related Methods
PATENT NUMBER: 10367064
PUBLICATION DATE: 12/13/2018

Abstract:

A semiconductor device may include a substrate, at least one memory array comprising a plurality of recessed channel array transistors (RCATs) on the substrate, and periphery circuitry adjacent the at least one memory array and including a plurality of complementary metal oxide (CMOS) transistors on the substrate. Each of the CMOS transistors may include spaced-apart source and drain regions in the substrate and defining a channel region therebetween, a superlattice extending between the source and drain regions in the channel region, and a gate over the superlattice and between the source and drain regions. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

See Patent

[#7446334] - Electronic Device Comprising Active Optical Devices with an Energy Band Engineered Superlattice
PATENT NUMBER: 7446334 
PUBLICATION DATE: 2/10/2005

Abstract:

An electronic device may include first and second integrated circuits including respective first and second active optical devices establishing an optical communications link therebetween. The first active optical device may include a superlattice including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Also, the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

See Patent

[#6741624] - Fabry-Perot Laser with Wavelength Control
PATENT NUMBER: 6741624
PUBLICATION DATE: 12/26/2002

Abstract:

A laser device, in particular a semiconductor laser, emitting optical radiation with a defined mode pattern can be produced from a standard Fabry-Perot (FP) laser by post-processing at the wafer level, i.e. before the wafer is separated into individual dies by cleaving/dicing. A sub-cavity is formed within the FP laser cavity. The sub-cavity has a predetermined length and is located between the FP facets. An aperiodic grating composed of a small number of contrast elements, typically less than 10, with predetermined inter-element separations and predetermined spacings relative to the sub-cavity is formed on or in the optical waveguide. The inter-element separations and the spacings relative to the sub-cavity produce a filtering function of the aperiodic grating for optical radiation propagating in the waveguide. The laser device is suitable for telecommunications applications due to its high side-mode-suppression ratio and narrow-linewidth.

See Patent

[#7202494] - FinFET Including a Superlattice
PATENT NUMBER: 7202494
PUBLICATION DATE: 12/28/2006

Abstract:

A semiconductor device may include at least one fin field-effect transistor (FINFET) comprising a fin, source and drain regions adjacent opposite ends of the fin, and a gate overlying the fin. The fin may include at least one superlattice including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

See Patent

[#10580867] - FinFET Including Source And Drain Regions With Dopant Diffusion Blocking Superlattice Layers To Reduce Contact Resistance
PATENT NUMBER: 10580867
PUBLICATION DATE: n/a

Abstract:

A FINFET may include a semiconductor fin, spaced apart source and drain regions in the semiconductor fin with a channel region extending therebetween, and at least one dopant diffusion blocking superlattice dividing at least one of the source and drain regions into a lower region and an upper region with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a gate on the channel region.

See Patent

[#7279699] - Integrated Circuit Comprising a Waveguide Having an Energy Band Engineered Superlattice
PATENT NUMBER: 7279699
PUBLICATION DATE: 2/10/2005

Abstract:

An integrated circuit may include at least one active optical device and a waveguide coupled thereto. The waveguide may include a superlattice including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

See Patent

[#7432524] - Integrated Circuit Comprising an Active Optical Device Having an Energy Band Engineered Superlattice
PATENT NUMBER: 7432524 
PUBLICATION DATE: 2/10/2005

Abstract:

An integrated circuit may include at least one active optical device including a superlattice including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The integrated circuit may further include a waveguide coupled to the at least one active optical device.

See Patent

[#10763370] - Inverted T Channel Field Effect Transistor (ITFET) Including A Superlattice
PATENT NUMBER: 10763370 
PUBLICATION DATE: 10/17/2019

Abstract:

A semiconductor device may include a substrate and an inverted T channel on the substrate and including a superlattice. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include source and drain regions on opposing ends of the inverted T channel, and a gate overlying the inverted T channel between the source and drain regions.

See Patent

[#10840337] - Method For Making A FinFET Having Reduced Contact Resistance
PATENT NUMBER: 10840337
PUBLICATION DATE: 5/21/2020

Abstract:

A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The method may further include forming a gate on the channel region, depositing at least one metal layer on the upper region, and applying heat to move upward non-semiconductor atoms from the non-semiconductor monolayers to react with the at least one metal layer to form a contact insulating interface between the upper region and adjacent portions of the at least one metal layer.

See Patent

[#10854717] - Method For Making A FinFET Including Source And Drain Dopant Diffusion Blocking Superlattices To Reduce Contact Resistance
PATENT NUMBER: 10854717
PUBLICATION DATE: 5/21/2020

Abstract:

A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice, with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.

See Patent

[#7700447] - Method for Making a Semiconductor Device Comprising a Lattice Matching Layer
PATENT NUMBER: 7700447 
PUBLICATION DATE: 8/23/2007

Abstract:

A method for making a semiconductor device which may include forming a first monocrystalline layer comprising a first material having a first lattice constant, a second monocrystalline layer including a second material having a second lattice constant different than the first lattice constant, and a lattice matching layer between the first and second monocrystalline layers and comprising a superlattice. More particularly, the superlattice may include a plurality of groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. Furthermore, the at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween.

See Patent

[#7018900] - Method for Making a Semiconductor Device Comprising a Superlattice Channel Vertically Stepped above Source and Drain Regions
PATENT NUMBER: 7018900 
PUBLICATION DATE: 4/28/2005

Abstract:

A method for making a semiconductor device may include providing a semiconductor substrate and forming at least one metal oxide semiconductor field-effect transistor (MOSFET). The at least one MOSFET may be formed by forming a superlattice channel including a plurality of stacked groups of layers on the semiconductor substrate. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor. The method may further include forming a gate overlying the superlattice channel, and forming source and drain regions in the semiconductor substrate on opposing sides of the superlattice channel so that the superlattice channel has upper surface portions vertically stepped above adjacent upper surface portions of the source and drain regions.

See Patent

[#7446002] - Method for Making a Semiconductor Device Comprising a Superlattice Dielectric Interface Layer
PATENT NUMBER: 7446002 
PUBLICATION DATE: 1/26/2006

Abstract:

A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers adjacent a substrate. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a high-K dielectric layer on the electrode layer, and forming an electrode layer on the high-K dielectric layer and opposite the superlattice.

See Patent

[#10879357] - Method For Making A Semiconductor Device Having A Hyper-Abrupt Junction Region Including A Superlattice
PATENT NUMBER: 10879357 
PUBLICATION DATE: 1/21/2021

Abstract:

A method for making semiconductor device may include forming a hyper-abrupt junction region on a substrate and including a first semiconductor layer having a first conductivity type, a superlattice layer on the first semiconductor layer, and a second semiconductor layer on the superlattice layer and having a second conductivity type different than the first conductivity type. The first, second, and the superlattice layers may be U-shaped. The method may further include forming a gate dielectric layer on the second semiconductor layer of the hyper-abrupt junction region, forming a gate electrode on the gate dielectric layer, and forming spaced apart source and drain regions adjacent the hyper-abrupt junction region.

See Patent

[#7491587] - Method for Making a Semiconductor Device Having a Semiconductor-On-Insulator (SOI) Configuration And Including a Superlattice on a Thin Semiconductor Layer
PATENT NUMBER: 7491587 
PUBLICATION DATE: 12/28/2006

Abstract:

A method for making a semiconductor device may include forming an insulating layer on a substrate, and forming a semiconductor layer on the insulating layer on a side thereof opposite the substrate. The method may further include forming a superlattice on the semiconductor layer on a side thereof opposite the insulating layer. The superlattice may include a plurality of stacked groups of layers, with each group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. Moreover, the at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions.

See Patent

[#10593761] - Method For Making A Semiconductor Device Having Reduced Contact Resistance
PATENT NUMBER: 10593761 
PUBLICATION DATE: n/a

Abstract:

A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The method may further include forming a gate on the channel region, depositing at least one metal layer on the upper region, and applying heat to move upward non-semiconductor atoms from the non-semiconductor monolayers to react with the at least one metal layer to form a contact insulating interface between the upper region and adjacent portions of the at least one metal layer.

See Patent

[#7265002] - Method for Making a Semiconductor Device Including a MOSFET Having a Band-engineered Superlattice with a Semiconductor Cap Layer Providing a Channel
PATENT NUMBER: 7265002 
PUBLICATION DATE: 8/11/2005

Abstract:

A method for making a semiconductor device may include providing a substrate, and forming at least one MOSFET adjacent the substrate by forming a superlattice including a plurality of stacked groups of layers and a semiconductor cap layer on an uppermost group of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming source, drain, and gate regions defining a channel through at least a portion of the semiconductor cap layer.

See Patent

[#10249745] - Method For Making A Semiconductor Device Including A Resonant Tunneling Diode Structure Having A Superlattice
PATENT NUMBER: 10249745 
PUBLICATION DATE: 2/8/2018

Abstract:

A method for making a semiconductor device may include forming at least one double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, and forming a first barrier layer on the first doped semiconductor layer and including a superlattice. The superlattice may include stacked groups of layers, each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming an intrinsic semiconductor layer on the first barrier layer, forming a second barrier layer on the intrinsic semiconductor layer, and forming a second doped semiconductor layer on the second superlattice layer.

See Patent

[#10170604] - Method For Making A Semiconductor Device Including A Resonant Tunneling Diode With Electron Mean Free Path Control Layers
PATENT NUMBER: 10170604 
PUBLICATION DATE: 2/8/2018

Abstract:

A method for making a semiconductor device may include forming at least one a double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, and a forming first barrier layer on the first doped semiconductor layer and including a superlattice. The method may further include forming a first intrinsic semiconductor layer on the first barrier layer, forming a second barrier layer on the first intrinsic semiconductor layer and also comprising the superlattice, forming a second intrinsic semiconductor layer on the second barrier layer, and forming a third barrier layer on the second intrinsic semiconductor layer and also comprising the superlattice. The method may further include forming a third intrinsic semiconductor layer on the third barrier layer, forming a fourth barrier layer on the third intrinsic semiconductor layer, and forming a second doped semiconductor layer on the fourth barrier layer.

See Patent

[#11094818] -Method for making a semiconductor device including a superlattice and an asymmetric channel and related methods
PATENT NUMBER: 11094818 
PUBLICATION DATE: 8/17/2021

Abstract:

A method for making a semiconductor device may include forming spaced apart first and second doped regions in a substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The method may further include forming a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a gate overlying the asymmetric channel.

See Patent

[#11075078] -Method for making a semiconductor device including a superlattice within a recessed etch
PATENT NUMBER: 11075078 
PUBLICATION DATE: 7/27/2021

Abstract:

A method for making a semiconductor device may include forming an isolation region adjacent an active region in a semiconductor substrate, and selectively etching the active region so that an upper surface of the active region is below an adjacent surface of the isolation region and defining a stepped edge therewith. The method may further include forming a superlattice overlying the active region. The superlattice may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

See Patent

[#7045377] - Method for Making a Semiconductor Device Including a Superlattice and Adjacent Semiconductor Layer With Doped Regions Defining a Semiconductor Junction
PATENT NUMBER: 7045377 
PUBLICATION DATE: 8/4/2005

Abstract:

A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a semiconductor layer adjacent the superlattice and comprising at least one first region therein including a first conductivity type dopant. At least one second region may be formed in the superlattice including a second conductivity type dopant to define, with the at least one first region, at least one semiconductor junction.

See Patent

[#7229902] - Method for Making a Semiconductor Device Including a Superlattice With Regions Defining a Semiconductor Junction
PATENT NUMBER: 7229902
PUBLICATION DATE: 8/4/2005

Abstract:

A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming at least one pair of oppositely-doped regions in the superlattice defining at least one semiconductor junction.

See Patent

[#7153763] - Method for Making a Semiconductor Device Including Band-engineered Superlattice Using Intermediate Annealing
PATENT NUMBER: 7153763 
PUBLICATION DATE: 12/8/2005

Abstract:

A method for making a semiconductor device may include forming a superlattice including a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include performing at least one anneal prior to completing forming of the superlattice.

See Patent

[#10727049] - Method For Making A Semiconductor Device Including Compound Semiconductor Materials And An Impurity And Point Defect Blocking Superlattice
PATENT NUMBER: 10727049 
PUBLICATION DATE: 9/12/2019

Abstract:

A method for making a semiconductor device may include forming a recess in a substrate including a first Group IV semiconductor, forming an active layer comprising a Group III-V semiconductor within the recess, and forming a buffer layer between the substrate and active layer and comprising a second Group IV semiconductor. The method may further include forming an impurity and point defect blocking superlattice layer adjacent the buffer layer.

See Patent

[#10879356] - Method For Making A Semiconductor Device Including Enhanced Contact Structures Having A Superlattice
PATENT NUMBER: 10879356 
PUBLICATION DATE: 9/12/2019

Abstract:

A method for making a semiconductor device may include forming a trench in a semiconductor substrate, and forming a superlattice liner covering bottom and sidewall portions of the trench. The superlattice liner may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a semiconductor cap layer on the superlattice liner and having a dopant constrained therein by the superlattice liner, and forming a conductive body within the trench.

See Patent

[#10741436] - Method For Making A Semiconductor Device Including Non-Monocrystalline Stringer Adjacent A Superlattice-STI Interface
PATENT NUMBER: 10741436 
PUBLICATION DATE: 2/21/2019

Abstract:

A method for making a semiconductor device may include forming first and second spaced apart shallow trench isolation (STI) regions in a semiconductor substrate, and forming a superlattice on the semiconductor substrate and extending between the first and second STI regions. The superlattice may include stacked groups of layers, each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a first semiconductor stringer comprising a non-monocrystalline body at an interface between a first end of the superlattice and the first STI region, and forming a gate above the superlattice.

See Patent

[#7535041] - Method for Making a Semiconductor Device Including Regions of Band-Engineered Semiconductor Superlattice to Reduce Device-On Resistance
PATENT NUMBER: 7535041 
PUBLICATION DATE: 1/18/2007

Abstract:

A method for making a semiconductor device which may include providing a substrate having a plurality of spaced apart superlattices therein, and forming source and drain regions in the substrate defining a channel region therebetween and with the plurality of spaced apart superlattices in the channel and/or drain regions. Each superlattice may include a plurality of stacked groups of layers, with each group including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. Moreover, the at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions.

See Patent

[#7812339] - Method for Making a Semiconductor Device Including Shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures
PATENT NUMBER: 7812339 
PUBLICATION DATE: 10/23/2008

Abstract:

A semiconductor device may include a semiconductor substrate having a surface, a shallow trench isolation (STI) region in the semiconductor substrate and extending above the surface thereof, and a superlattice layer adjacent the surface of the semiconductor substrate and comprising a plurality of stacked groups of layers. More particularly, each group of layers of the superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, at least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer. The semiconductor device may further include a lateral spacer between the superlattice layer and the STI region and which may include a lower non-monocrystalline semiconductor superlattice portion and an upper dielectric portion.

See Patent

[#7514328] - Method for Making a Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice Therebetween
PATENT NUMBER: 7514328 
PUBLICATION DATE: 11/30/2006

Abstract:

A method for making a semiconductor device may include forming a plurality of shallow trench isolation (STI) regions in a semiconductor substrate. Further, a plurality of layers may be deposited over the substrate to define respective superlattices over the substrate between adjacent STI regions and to define respective non-monocrystalline regions over the STI regions. The method may further include selectively removing at least portions of the non-monocrystalline regions using at least one active area (AA) mask.\\\\\\\\\\\\\\\\

See Patent

[#10191105] - Method For Making A Semiconductor Device Including Threshold Voltage Measurement Circuitry
PATENT NUMBER: 10191105 
PUBLICATION DATE: 2/22/2018

Abstract:

A method for making a semiconductor device may include forming active circuitry on a substrate including differential transistor pairs, and forming threshold voltage test circuitry on the substrate. The threshold voltage test circuitry may include a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, with each test transistor having a respective input and output, and at least one gain stage configured to amplify a difference between the outputs of the differential test transistors for measuring a threshold voltage thereof. The differential transistor pairs and the pair of differential test transistors each includes spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region. Moreover, each of the channel regions may include a superlattice.

See Patent

[#10937888] - Method For Making A Varactor With A Hyper-Abrupt Junction Region Including Spaced-Apart Superlattices
PATENT NUMBER: 10937888 
PUBLICATION DATE: 1/21/2021

Abstract:

A method for making a semiconductor device may include forming a hyper-abrupt junction region above a substrate and including a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and a second superlattice layer on the second semiconductor layer. The method may further include forming a first contact coupled to the hyper-abrupt junction region and a second contact coupled to the substrate to define a varactor. The first and second superlattices may each include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

See Patent

[#10868120] - Method For Making A Varactor With Hyper-Abrupt Junction Region Including A Superlattice
PATENT NUMBER: 10868120 
PUBLICATION DATE: 12/15/2020

Abstract:

A method for making a semiconductor device may include forming a hyper-abrupt junction region on a substrate. The hyper-abrupt junction region may include a first semiconductor layer having a first conductivity type, a superlattice layer on the first semiconductor layer, and a second semiconductor layer on the superlattice layer and having a second conductivity type different than the first conductivity type. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a first contact coupled to the hyper-abrupt junction regions, and forming a second contact coupled to the substrate to define a varactor.

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[#7517702] - Method for Making an Electronic Device Including a Poled Superlattice Having a Net Electrical Dipole Moment
PATENT NUMBER: 7517702 
PUBLICATION DATE: 7/12/2007

Abstract:

A method for making an electronic device may include forming a poled superlattice comprising a plurality of stacked groups of layers and having a net electrical dipole moment. Each group of layers of the poled superlattice may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The method may further include coupling at least one electrode to the poled superlattice.

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[#7109052] - Method for Making an Integrated Circuit Comprising a Waveguide Having an Energy Band Engineered Superlattice
PATENT NUMBER: 7109052 
PUBLICATION DATE: 2/10/2005

Abstract:

A method for making an integrated circuit may include forming at least one active optical device and a waveguide coupled thereto. The waveguide may include a superlattice including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

See Patent

[#10461118] - Method for Making CMOS Image Sensor Including Photodiodes With Overlying Superlattices to Reduce Crosstalk
PATENT NUMBER: 10461118 
PUBLICATION DATE: 6/20/2019

Abstract:

A method for making a CMOS image sensor may include forming a plurality of laterally adjacent photodiodes on a semiconductor substrate having a first conductivity types by forming a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type, forming a first well around a periphery of the retrograde well also having the second conductivity type, and forming a second well within the retrograde well having the first conductivity type. Furthermore, first and second superlattices may be respectively formed overlying each of the first and second wells, with each of the first and second superlattices comprising a plurality of stacked groups of layers, and each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

See Patent

[#10529768] - Method For Making Cmos Image Sensor Including Pixels With Read Circuitry Having A Superlattice
PATENT NUMBER: 10529768 
PUBLICATION DATE: 6/20/2019

Abstract:

A method for making a CMOS image sensor may include forming an active pixel sensor array including pixels, each including a photodiode and read circuitry coupled to the photodiode and including transistors defining a 4T cell arrangement. At least one of the transistors may include a first semiconductor layer and a superlattice on the first semiconductor layer including a plurality of stacked groups of layers, with each group including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The transistor(s) may also include a second semiconductor layer on the superlattice, spaced apart source and drain regions in the second semiconductor layer defining a channel therebetween, and a gate comprising a gate insulating layer on the second semiconductor layer and a gate electrode on the gate insulating layer.

See Patent

[#10608027] - Method For Making CMOS Image Sensor Including Stacked Semiconductor Chips And Image Processing Circuitry Including A Superlattice
PATENT NUMBER: 10608027 
PUBLICATION DATE: 6/20/2019

Abstract:

A method for making a CMOS image sensor may include forming a first semiconductor chip including an array of image sensor pixels and readout circuitry electrically connected thereto, forming a second semiconductor chip including image processing circuitry electrically connected to the readout circuitry, and coupling the first semiconductor chip and the second semiconductor chip in a stack. The processing circuitry may include a plurality of transistors each including spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate including a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.

See Patent

[#10608043] - Method For Making Cmos Image Sensor Including Stacked Semiconductor Chips And Readout Circuitry Including A Superlattice
PATENT NUMBER: 10608043 
PUBLICATION DATE: 6/20/2019

Abstract:

A method for making a CMOS image sensor may include forming a first semiconductor chip including an array of image sensor pixels and readout circuitry electrically connected thereto, forming a second semiconductor chip comprising image processing circuitry electrically connected to the readout circuitry, and coupling the first semiconductor chip and the second semiconductor chip together in a stack. The readout circuitry may include a plurality of transistors each including spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate including a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.

See Patent

[#10361243] - Method For Making CMOS Image Sensor Including Superlattice To Enhance Infrared Light Absorption
PATENT NUMBER: 10361243 
PUBLICATION DATE: 6/20/2019

Abstract:

A method for making a CMOS image sensor may include forming a plurality of laterally adjacent infrared (IR) photodiode structures on a semiconductor substrate having a first conductivity type. Forming each IR photodiode structure may include forming a superlattice on the semiconductor substrate including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. The superlattice may have the first conductivity type. A semiconductor layer may be formed on the superlattice, along with a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well above the retrograde well having the first conductivity type.

See Patent

[#10396223] - Method For Making Cmos Image Sensor With Buried Superlattice Layer To Reduce Crosstalk
PATENT NUMBER: 10396223 
PUBLICATION DATE: 6/20/2019

Abstract:

A method for making a CMOS image sensor may include forming a superlattice on a semiconductor substrate having a first conductivity type, with the superlattice including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a plurality of laterally adjacent photodiodes on the superlattice. Each photodiode may include a semiconductor layer on the superlattice and having a first conductivity type dopant and with a lower dopant concentration than the semiconductor substrate, a retrograde well extending downward into the semiconductor layer and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type.

See Patent

[#10636879] - Method For Making Dram With Recessed Channel Array Transistor (RCAT) Including A Superlattice
PATENT NUMBER: 10636879 
PUBLICATION DATE: 12/13/2018

Abstract:

A method for making a semiconductor device may include forming at least one memory array including a plurality of recessed channel array transistors (RCATs) on a substrate, and forming periphery circuitry adjacent the at least one memory array and comprising a plurality of complementary metal oxide (CMOS) transistors on the substrate. Each of the CMOS transistors may include spaced-apart source and drain regions in the substrate and defining a channel region therebetween, and a first superlattice extending between the source and drain regions in the channel region. The first superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may be over the first superlattice and between the source and drain regions.

See Patent

[#9721790] - Method for Making Enhanced Semiconductor Structures in Single Wafer Processing Chamber with Desired Uniformity Control
PATENT NUMBER: 9721790 
PUBLICATION DATE: 12/8/2016

Abstract:

A method for processing a semiconductor wafer in a single wafer processing chamber may include heating the single wafer processing chamber to a temperature in a range of 650-700° C., and forming at least one superlattice on the semiconductor wafer within the heated single wafer processing chamber by depositing silicon and oxygen to form a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions. Depositing the oxygen may include depositing the oxygen using an N2O gas flow.

See Patent

[#7288457] - Method for Making Semiconductor Device Comprising a Superlattice with Upper Portions Extending above Adjacent Upper Portions of Source and Drain Regions
PATENT NUMBER: 7288457 
PUBLICATION DATE: 6/2/2005

Abstract:

A method for making a semiconductor device may include providing a semiconductor substrate and forming at least one MOSFET by forming spaced apart source and drain regions and a superlattice on the substrate so that the superlattice is between the source and drain regions. The superlattice may include a plurality of stacked groups of layers. The superlattice may have upper portions extending above adjacent upper portions of the source and drain regions, and lower portions contacting the source and drain regions so that a channel is defined in lower portions of the superlattice. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor. The method may further include forming a gate overlying the superlattice.

See Patent

[#6830964] - Method for Making Semiconductor Device Including Band-engineered Superlattice
PATENT NUMBER: 6830964 
PUBLICATION DATE: 12/30/2004

Abstract:

A method is for making a semiconductor device by forming a superlattice that, in turn, includes a plurality of stacked groups of layers. The method may also include forming regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions so that the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise occur. The superlattice may also have a common energy band structure therein.

See Patent

[#6878576] - Method for Making Semiconductor Device Including Band-engineered Superlattice
PATENT NUMBER: 6878576 
PUBLICATION DATE: n/a

Abstract:

A method is for making a semiconductor device by forming a superlattice that, in turn, includes a plurality of stacked groups of layers. The method may also include forming regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions so that the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise occur. The superlattice may also have a common energy band structure therein.

See Patent

[#6833294] - Method for Making Semiconductor Device Including Band-engineered Superlattice
PATENT NUMBER: 6833294 
PUBLICATION DATE: 12/30/2004

Abstract:

A method is for making a semiconductor device by forming a superlattice that, in turn, includes a plurality of stacked groups of layers. The method may also include forming regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions so that the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise occur. The superlattice may also have a common energy band structure therein.

See Patent

[#7033437] - Method for Making Semiconductor Device Including Band-engineered Superlattice
PATENT NUMBER: 7033437 
PUBLICATION DATE: 12/30/2004

Abstract:

A method is for making a semiconductor device by forming a superlattice that, in turn, includes a plurality of stacked groups of layers. The method may also include forming regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions so that the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise occur. The superlattice may also have a common energy band structure therein.

See Patent

[#10840335] - Method For Making Semiconductor Device Including Body Contact Dopant Diffusion Blocking Superlattice To Reduce Contact Resistance
PATENT NUMBER: 10840335 
PUBLICATION DATE: 5/21/2020

Abstract:

A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween, and forming a gate on the channel region. The method may further include forming a body contact in the semiconductor layer and including a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and an second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region. The body contact dopant diffusion blocking superlattice may include a respective plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

See Patent

[#10818755] - Method For Making Semiconductor Device Including Source/Drain Dopant Diffusion Blocking Superlattices To Reduce Contact Resistance
PATENT NUMBER: 10818755 
PUBLICATION DATE: 5/21/2020

Abstract:

A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.

See Patent

[#10937868] - Method For Making Semiconductor Devices With Hyper-Abrupt Junction Region Including Spaced-Apart Superlattices
PATENT NUMBER: 10937868 
PUBLICATION DATE: 1/21/2021

Abstract:

A method for making a semiconductor device may include forming a hyper-abrupt junction region above a substrate and including a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and a second superlattice layer on the second semiconductor layer. The method may further include forming a gate dielectric layer on the second superlattice layer of the hyper-abrupt junction region, forming a gate electrode on the gate dielectric layer, and forming spaced apart source and drain regions adjacent the hyper-abrupt junction region.

See Patent

[#10811498] - Method For Making Superlattice Structures With Reduced Defect Densities
PATENT NUMBER: 10811498 
PUBLICATION DATE: 3/5/2020

Abstract:

A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, forming at least one of the base semiconductor portions may include overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.

See Patent

[#10381242] - Method of a Semiconductor wafer including a Superlattice as a Gettering layer and related methods
PATENT NUMBER: 10381242 
PUBLICATION DATE: 11/22/2018

Abstract:

A semiconductor processing method may include forming a superlattice gettering layer on a front side of a semiconductor substrate having a first thickness, epitaxially growing an active semiconductor layer on the superlattice gettering layer opposite the semiconductor substrate, forming at least one semiconductor device in the active semiconductor layer, and forming at least one metal interconnect layer on the active layer, and at least one metal through-via extending from the at least one metal interconnect layer into the semiconductor substrate. The method may further include thinning the semiconductor substrate from a back side thereof to a second thickness less than the first thickness, and thinning the semiconductor substrate. The superlattice gettering layer getters metal ions released by the forming of the at least one metal interconnect layer and at least one metal through-via, and thinning the substrate.

See Patent

[#7863066] - Method of Making a Multiple-Wavelength Opto-electronic Device Including a Superlattice
PATENT NUMBER: 7863066 
PUBLICATION DATE: 8/21/2008

Abstract:

A method for making a multiple-wavelength opto-electronic device which may include providing a substrates and forming a plurality of active optical devices to be carried by the substrate and operating at different respective wavelengths. Moreover, each optical device may include a superlattice comprising a plurality of stacked groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon.

See Patent

[#10109479] - Method Of Making A Semiconductor Device With A Buried Insulating Layer Formed By Annealing A Superlattice
PATENT NUMBER: 10109479 
PUBLICATION DATE: n/a

Abstract:

A method for making a semiconductor device may include forming a superlattice on a semiconductor substrate including a respective plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Further, at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The method may further include epitaxially forming a semiconductor layer on the superlattice, and annealing the superlattice to form a buried insulating layer in which the at least some semiconductor atoms are no longer chemically bound together through the at least one non-semiconductor monolayer therebetween.

See Patent

[#9558939] - Methods for Making a Semiconductor Device Including Atomic Layer Structures Using N2O as an Oxygen Source
PATENT NUMBER: 9558939 
PUBLICATION DATE: n/a

Abstract:

A method for making a semiconductor device may include forming a plurality of spaced apart structures on a semiconductor substrate within a semiconductor processing chamber, with each structure including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base silicon monolayers defining a base semiconductor portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions. Furthermore, the oxygen monolayers may be formed using N2O as an oxygen source.

See Patent

[#7625767] - Methods of Making Spintronic Devices With Constrained Spintronic Dopant
PATENT NUMBER: 7625767 
PUBLICATION DATE: 10/11/2007

Abstract:

A method is for making a spintronic device and may include forming at least one superlattice and at least one electrical contact coupled thereto, with the at least one superlattice including a plurality of groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice, at least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor portions, and a spintronic dopant. The spintronic dopant may be constrained within the crystal lattice of the base semiconductor portion by the at least one non-semiconductor monolayer. In some embodiments, the repeating structure of a superlattice may not be needed.

See Patent

[#7586165] - Microelectromechanical Systems (MEMS) Device Including a Superlattice
PATENT NUMBER: 7586165 
PUBLICATION DATE: 10/12/2006

Abstract:

A microelectromechanical system (MEMS) device may include a substrate and at least one movable member supported by the substrate. The at least one movable member may include a superlattice including a plurality of stacked groups of layers with each group of layers of the superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

See Patent

[#7880161] - Multiple-Wavelength Opto-electronic Device Including a Superlattice
PATENT NUMBER: 7880161 
PUBLICATION DATE: 8/21/2008

Abstract:

A multiple-wavelength opto-electronic device may include a substrate and a plurality of active optical devices carried by the substrate and operating at different respective wavelengths. Each optical device may include a superlattice comprising a plurality of stacked groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon.

See Patent

[#8389974] - Multiple-Wavelength Opto-electronic Device Including a Superlattice
PATENT NUMBER: 8389974 
PUBLICATION DATE: 8/11/2011

Abstract:

A multiple-wavelength opto-electronic device may include a substrate and a plurality of active optical devices carried by the substrate and operating at different respective wavelengths. Each optical device may include a superlattice comprising a plurality of stacked groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon.

See Patent

[#6993222] - Optical Filter Device with Aperiodically Arranged Grating Elements
PATENT NUMBER: 6993222 
PUBLICATION DATE: 10/21/2004

Abstract:

A method for producing aperiodic gratings and waveguides with aperiodic gratings uses a simulated annealing process that starts with a random configuration of grating elements and iteratively computes a spectral response from a Fourier transform of the configuration of grating elements obtained in successive iterations. A cost function is computed as a convergence criterion. The aperiodic grating can be used, for example, as a filter in WDM applications.

See Patent

[#7718996] - Semiconductor Device Comprising a Lattice Matching Layer
PATENT NUMBER: 7718996 
PUBLICATION DATE: 8/23/2007

Abstract:

A semiconductor device may include a first monocrystalline layer comprising a first material having a first lattice constant. A second monocrystalline layer may include a second material having a second lattice constant different than the first lattice constant. The device may also include a lattice matching layer between the first and second monocrystalline layers and comprising a superlattice. The superlattice may include a plurality of groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween.

See Patent

[#7436026] - Semiconductor Device Comprising a Superlattice Channel Vertically Stepped above Source and Drain Regions
PATENT NUMBER: 7436026 
PUBLICATION DATE: 4/28/2005

Abstract:

A semiconductor device may include a semiconductor substrate and at least one metal oxide semiconductor field-effect transistor (MOSFET). The at least one MOSFET may include spaced apart source and drain regions in the semiconductor substrate, and a superlattice channel including a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions. The superlattice channel may have upper surface portions vertically stepped above adjacent upper surface portions of the source and drain regions. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor. The at least one MOSFET may additionally include a gate overlying the superlattice channel.

See Patent

[#7279701] - Semiconductor Device Comprising a Superlattice with Upper Portions Extending above Adjacent Upper Portions of Source and Drain Regions
PATENT NUMBER: 7279701 
PUBLICATION DATE: 5/26/2005

Abstract:

A semiconductor device may include a semiconductor substrate and at least one metal oxide semiconductor field-effect transistor (MOSFET). The MOSFET may include spaced apart source and drain regions on the semiconductor substrate, and a superlattice including a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions. The superlattice may have upper portions extending above adjacent upper portions of the source and drain regions, and lower portions contacting the source and drain regions so that a channel is defined in lower portions of said superlattice. Furthermore, each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor. A gate may overly the superlattice.

See Patent

[#7586116] - Semiconductor Device Having a Semiconductor-on-insulator Configuration and a Superlattice
PATENT NUMBER: 7586116 
PUBLICATION DATE: 1/23/2006

Abstract:

A semiconductor device may include a substrate, an insulating layer adjacent the substrate, and a semiconductor layer adjacent a face of the insulating layer opposite the substrate. The device may further include source and drain regions on the semiconductor layer, a superlattice adjacent the semiconductor layer and extending between the source and drain regions to define a channel, and a gate overlying the superlattice. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

See Patent

[#7659539] - Semiconductor Device Including a Floating Gate Memory Cell with a Superlattice Channel
PATENT NUMBER: 7659539 
PUBLICATION DATE: 11/2/2006

Abstract: A semiconductor device may include a semiconductor substrate and at least one non-volatile memory cell. The at least one memory cell may include spaced apart source and drain regions, and a superlattice channel including a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon, which may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A floating gate may be adjacent the superlattice channel, and a control gate may be adjacent the second gate insulating layer.

See Patent

[#7531850] - Semiconductor Device Including a Memory Cell with Negative Differential Resistance (NDR) Device
PATENT NUMBER: 7531850 
PUBLICATION DATE: 9/14/2006

Abstract:

A semiconductor device may include at least one memory cell comprising a negative differential resistance (NDR) device and a control gate coupled thereto. The NDR device may include a superlattice including a plurality of stacked groups of layers, with each group of layers of the superlattice including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

See Patent

[#7928425] - Semiconductor Device Including a Metal-to-Semiconductor Superlattice Interface Layer and Related Methods
PATENT NUMBER: 7928425 
PUBLICATION DATE: 7/31/2008

Abstract:

A semiconductor device which may include a semiconductor layer, and a superlattice interface layer therebetween. The superlattice interface layer may include a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.

See Patent

[#7435988] - Semiconductor Device Including a MOSFET Having a Band-engineered Superlattice with a Semiconductor Cap Layer Providing a Channel
PATENT NUMBER: 7435988
PUBLICATION DATE: 8/11/2005

Abstract:

A semiconductor device may include a substrate and at least one MOSFET adjacent the substrate including a superlattice. The superlattice may include a plurality of stacked groups of layers and a semiconductor cap layer on an uppermost group of layers. Each group of layers of the superlattice may comprise a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The MOSFET may further include source, drain, and gate regions defining a channel through at least a portion of the semiconductor cap layer.

See Patent

[#10170603] - Semiconductor Device Including A Resonant Tunneling Diode Structure With Electron Mean Free Path Control Layers
PATENT NUMBER: 10170603 
PUBLICATION DATE: 2/8/2018

Abstract:

A semiconductor device including at least one double-barrier resonant tunneling diode (DBRTD) is provided. The at least one DBRTD may include a first doped semiconductor layer, and a first barrier layer on the first doped semiconductor layer and including a superlattice. The DBRTD may further include a first intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the first intrinsic semiconductor layer and also including the superlattice, a second intrinsic semiconductor layer on the second barrier layer, a third barrier layer on the second intrinsic semiconductor layer and also including the superlattice. A third intrinsic semiconductor layer may be on the third barrier layer, a fourth barrier layer may be on the third intrinsic semiconductor layer and also including the superlattice, a second doped semiconductor layer on the fourth barrier layer.

See Patent

[#7598515] - Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods
PATENT NUMBER: 7598515 
PUBLICATION DATE: 1/18/2007

Abstract:

A semiconductor device may include a strained superlattice layer including a plurality of stacked groups of layers, and a stress layer above the strained superlattice layer. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

See Patent

[#7531828] - Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions
PATENT NUMBER: 7531828 
PUBLICATION DATE: 1/18/2007

Abstract:

A semiconductor device may include at least one pair of spaced apart stress regions, and a strained superlattice layer between the at least one pair of spaced apart stress regions and including a plurality of stacked groups of layers. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

See Patent

[#7612366] - Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer
PATENT NUMBER: 7612366 
PUBLICATION DATE: 1/11/2007

Abstract:

A semiconductor device may include a stress layer and a strained superlattice layer above the stress layer and including a plurality of stacked groups of layers. More particularly, each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

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[#7227174] - Semiconductor Device Including a Superlattice and Adjacent Semiconductor Layer With Doped Regions Defining a Semiconductor Junction
PATENT NUMBER: 7227174 
PUBLICATION DATE: 8/4/2005

Abstract:

A semiconductor device may include a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The semiconductor device may further include a semiconductor layer adjacent the superlattice and comprising at least one first region therein including a first conductivity type dopant. The superlattice may also include at least one second region therein including a second conductivity type dopant to define, with the at least one first region, at least one semiconductor junction.

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[#9722046] - Semiconductor Device Including a Superlattice and Replacement Metal Gate Structure and Related Methods
PATENT NUMBER: 9722046 
PUBLICATION DATE: 5/26/2016

Abstract:

A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.

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[#10084045] - Semiconductor Device Including a Superlattice and Replacement Metal Gate Structure and Related Methods
PATENT NUMBER: 10084045 
PUBLICATION DATE: 10/19/2017

Abstract:

A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.

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[#10410880] - Semiconductor Device Including A Superlattice As A Gettering Layer
PATENT NUMBER: 10410880 
PUBLICATION DATE: 11/22/2018

Abstract:

A semiconductor device may include a semiconductor substrate having a front side and a back side opposite the front side, and a superlattice gettering layer on the front side of a semiconductor substrate. The superlattice gettering layer may include stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The device may further include an active semiconductor layer on the superlattice gettering layer opposite the semiconductor substrate, at least one semiconductor circuit in the active semiconductor layer, at least one metal interconnect layer on the active layer, and at least one metal through-via extending from the at least one metal interconnect layer to the back side of the semiconductor substrate. The superlattice gettering layer may further include gettered metal ions.

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[#7045813] - Semiconductor Device Including a Superlattice With Regions Defining a Semiconductor Junction
PATENT NUMBER: 7045813 
PUBLICATION DATE: 8/4/2005

Abstract:

A semiconductor device may include a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The superlattice may further include at least one pair of oppositely-doped regions therein defining at least one semiconductor junction.

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[#7034329] - Semiconductor Device Including Band-engineered Superlattice Having 3/1-5/1 Germanium Layer Structure
PATENT NUMBER: 7034329 
PUBLICATION DATE: 4/28/2005

Abstract:

A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. The device may also include regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Moreover, the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Accordingly, the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise be present.

See Patent

 

[#6958486] - Semiconductor Device Including Band-engineered Superlattice
PATENT NUMBER: 6958486 
PUBLICATION DATE: 12/30/2004

Abstract:

A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. The device may also include regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Moreover, the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Accordingly, the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise be present.

See Patent

 

[#6891188] - Semiconductor Device Including Band-engineered Superlattice
PATENT NUMBER: 6891188 
PUBLICATION DATE: 12/30/2004

Abstract:

A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. The device may also include regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Moreover, the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Accordingly, the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise be present.

See Patent

 

[#6952018] - Semiconductor Device Including Band-engineered Superlattice
PATENT NUMBER: 6952018 
PUBLICATION DATE: 12/30/2004

Abstract:

A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. The device may also include regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Moreover, the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Accordingly, the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise be present.

See Patent

 

[#6927413] - Semiconductor Device Including Band-engineered Superlattice
PATENT NUMBER: 6927413 
PUBLICATION DATE: 1/27/2005

Abstract:

A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. The device may also include regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Moreover, the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Accordingly, the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise be present.

See Patent

 

[#10847618] - Semiconductor Device Including Body Contact Dopant Diffusion Blocking Superlattice Having Reduced Contact Resistance
PATENT NUMBER: 10847618 
PUBLICATION DATE: 5/21/2020

Abstract:

A semiconductor device may include a semiconductor layer, spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and a gate on the channel region. The semiconductor device may further include a body contact in the semiconductor layer and comprising a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and an second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region. The body contact dopant diffusion blocking superlattice may include a respective plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

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[#10468245] - Semiconductor Device Including Compound Semiconductor Materials And An Impurity And Point Defect Blocking Superlattice
PATENT NUMBER: 10468245 
PUBLICATION DATE: 9/12/2019

Abstract:

A semiconductor device may include a substrate including a first Group IV semiconductor having a recess therein, an active layer comprising a Group III-V semiconductor within the recess, and a buffer layer between the substrate and active layer and comprising a second Group IV semiconductor. The semiconductor device may further include an impurity and point defect blocking superlattice layer adjacent the buffer layer.

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[#10777451] - Semiconductor Device Including Enhanced Contact Structures Having A Superlattice
PATENT NUMBER: 10777451 
PUBLICATION DATE: 9/12/2019

Abstract:

A semiconductor device may include a semiconductor substrate having a trench therein, and a superlattice liner at least partially covering bottom and sidewall portions of the trench. The superlattice liner may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a semiconductor cap layer on the superlattice liner and having a dopant constrained therein by the superlattice liner, and a conductive body within the trench.

See Patent

[#7303948] - Semiconductor Device Including MOSFET Having Band-Engineered Superlattice
PATENT NUMBER: 7303948 
PUBLICATION DATE: 8/25/2005

Abstract:

A semiconductor device includes a substrate, and at least one MOSFET adjacent the substrate. The MOSFET may include a superlattice channel that, in turn, includes a plurality of stacked groups of layers. The MOSFET may also include source and drain regions laterally adjacent the superlattice channel, and a gate overlying the superlattice channel for causing transport of charge carriers through the superlattice channel in a parallel direction relative to the stacked groups of layers. Each group of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions so that the superlattice channel may have a higher charge carrier mobility in the parallel direction than would otherwise occur.

See Patent

[#6897472] - Semiconductor Device Including MOSFET Having Band-engineered Superlattice
PATENT NUMBER: 6897472 
PUBLICATION DATE: 12/30/2004

Abstract:

A semiconductor device includes a substrate, and at least one MOSFET adjacent the substrate. The MOSFET may include a superlattice channel that, in turn, includes a plurality of stacked groups of layers. The MOSFET may also include source and drain regions laterally adjacent the superlattice channel, and a gate overlying the superlattice channel for causing transport of charge carriers through the superlattice channel in a parallel direction relative to the stacked groups of layers. Each group of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions so that the superlattice channel may have a higher charge carrier mobility in the parallel direction than would otherwise occur.

See Patent

[#7531829] - Semiconductor Device Including Regions of Band-Engineered Semiconductor Superlattice to Reduce Device-On Resistance
PATENT NUMBER: 7531829 
PUBLICATION DATE: 1/18/2007

Abstract:

A semiconductor device may include a substrate and spaced apart source and drain regions defining a channel region therebetween in the substrate. The substrate may have a plurality of spaced apart superlattices in the channel and/or drain regions. Each superlattice may include a plurality of stacked groups of layers, with each group including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions.

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[#10453945] - Semiconductor Device Including Resonant Tunneling Diode Structure Having A Superlattice
PATENT NUMBER: 10453945 
PUBLICATION DATE: 2/8/2018

Abstract:

A semiconductor device may include at least one double-barrier resonant tunneling diode (DBRTD). The at least one DBRTD may include a first doped semiconductor layer and a first barrier layer on the first doped semiconductor layer and including a superlattice. The superlattice may include stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one DBRTD may further include an intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the intrinsic semiconductor layer, and a second doped semiconductor layer on the second superlattice layer.

See Patent

[#10580866] - Semiconductor Device Including Source/Drain Dopant Diffusion Blocking Superlattices To Reduce Contact Resistance
PATENT NUMBER: 10580866 
PUBLICATION DATE: n/a

Abstract:

A semiconductor device may include a semiconductor layer, spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and at least one dopant diffusion blocking superlattice dividing at least one of the source and drain regions into a lower region and an upper region with the upper region having a same conductivity and higher dopant concentration than the lower region. The at least one dopant diffusion blocking superlattice comprising a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a gate on the channel region.

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[#10566191] - Semiconductor Device Including Superlattice Structures With Reduced Defect Densities
PATENT NUMBER: 10566191 
PUBLICATION DATE: 3/5/2020

Abstract: A semiconductor device may include a substrate and a superlattice on the substrate including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Furthermore, an upper portion of at least one of the base semiconductor portions adjacent the respective at least one non-semiconductor monolayer may have a defect density less than or equal to 1×105/cm2.

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[#10107854] - Semiconductor Device Including Threshold Voltage Measurement Circuitry
PATENT NUMBER: 10107854 
PUBLICATION DATE: 2/22/2018

Abstract: A semiconductor device may include a substrate, active circuitry on the substrate and including differential transistor pairs, and threshold voltage test circuitry on the substrate. The threshold voltage test circuitry may include a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, with each test transistor having a respective input and output, and at least one gain stage configured to amplify a difference between the outputs of the differential test transistors for measuring a threshold voltage thereof. The differential transistor pairs and the pair of differential test transistors may each include spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region. Each of the channel regions may include a superlattice.

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[#10884185] - Semiconductor Device Including Vertically Integrated Optical And Electronic Devices And Comprising A Superlattice
PATENT NUMBER: 10884185 
PUBLICATION DATE: 10/17/2019

Abstract:

A semiconductor device may include a substrate having waveguides thereon, and a superlattice overlying the substrate and waveguides. The superlattice may include stacked groups of layers, with each group of layers comprising a stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include an active device layer on the superlattice including at least one active semiconductor device.

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[#7781827] - Semiconductor Device with a Vertical Mosfet Including a Superlattice and Related Methods
PATENT NUMBER: 7781827 
PUBLICATION DATE: 7/31/2008

Abstract:

A semiconductor device may include at least one vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) on a substrate. The vertical MOSFET may include at least one superlattice including a plurality of laterally stacked groups of layers transverse to the substrate. The vertical MOSFET(s) may further include a gate laterally adjacent the superlattice, and regions vertically above and below the superlattice and cooperating with the gate for causing transport of charge carriers through the superlattice in the vertical direction. Each group of layers of the superlattice may include stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.

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[#10840336] - Semiconductor Device With Metal-Semiconductor Contacts Including Oxygen Insertion Layer To Constrain Dopants And Related Methods
PATENT NUMBER: 10840336 
PUBLICATION DATE: 5/21/2020

Abstract:

A semiconductor device may include a semiconductor layer and at least one contact in the semiconductor layer. The contact may include at least one oxygen monolayer constrained within a crystal lattice of adjacent semiconductor portions of the semiconductor layer and spaced apart from a surface of the semiconductor layer by between one and four monolayers, and a metal layer on the surface of the semiconductor layer above the at least one oxygen monolayer. The semiconductor portion between the oxygen monolayer and the metal layer may have a dopant concentration of 1×1021 atoms/cm3 or greater.

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[#10825901] - Semiconductor Devices Including Hyper-Abrupt Junction Region Including A Superlattice
PATENT NUMBER: 10825901 
PUBLICATION DATE: 11/3/2020

Abstract:

A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate. The hyper-abrupt junction region may include a first semiconductor layer having a first conductivity type, a superlattice layer on the first semiconductor layer, and a second semiconductor layer on the superlattice layer and having a second conductivity type different than the first conductivity type. The first, second, and the superlattice layers may be U-shaped. The semiconductor device may further include a gate dielectric layer on the second semiconductor layer of the hyper-abrupt junction region, a gate electrode on the gate dielectric layer, and spaced apart source and drain regions adjacent the hyper-abrupt junction region.

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[#9406753] - Semiconductor Devices Including Superlattice Depletion Layer Stack and Related Methods
PATENT NUMBER: 9406753 
PUBLICATION DATE: 5/28/2015

Abstract:

A semiconductor device may include an alternating stack of superlattice and bulk semiconductor layers on a substrate, with each superlattice layer including a plurality of stacked group of layers, and each group of layers of the superlattice layer including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include spaced apart source and drain regions in an upper bulk semiconductor layer of the alternating stack of superlattice and bulk semiconductor layers, and a gate on the upper bulk semiconductor layer between the spaced apart source and drain regions.

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[#9716147] - Semiconductor Devices with Enhanced Deterministic Doping and Related Methods
PATENT NUMBER: 9716147 
PUBLICATION DATE: 12/10/2015

Abstract:

A method for making a semiconductor device may include forming a plurality of stacked groups of layers on a semiconductor substrate, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include implanting a dopant in the semiconductor substrate beneath the plurality of stacked groups of layers in at least one localized region, and performing an anneal of the plurality of stacked groups of layers and semiconductor substrate and with the plurality of stacked groups of layers vertically and horizontally constraining the dopant in the at least one localized region.

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[#10170560] - Semiconductor Devices with Enhanced Deterministic Doping and Related Methods
PATENT NUMBER: 10170560 
PUBLICATION DATE: 10/12/2017

Abstract:

A method for making a semiconductor device may include forming a plurality of stacked groups of layers on a semiconductor substrate, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include implanting a dopant in the semiconductor substrate beneath the plurality of stacked groups of layers in at least one localized region, and performing an anneal of the plurality of stacked groups of layers and semiconductor substrate and with the plurality of stacked groups of layers vertically and horizontally constraining the dopant in the at least one localized region.

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[#9941359] - Semiconductor Devices with Superlattice and Punch through Stop (PTS) Layers at Different Depths and Related Methods
PATENT NUMBER: 9941359 
PUBLICATION DATE: 11/17/2016

Abstract:

A semiconductor device may include a semiconductor substrate and first transistors having a first operating voltage. Each first transistor may include a first channel and a first punch-through stop (PTS) layer in the semiconductor substrate, and the first PTS layer may be at a first depth below the first channel. The semiconductor device may further include second transistors having a second operating voltage higher than the first operating voltage. Each second transistor may include a second channel and a second PTS layer in the semiconductor substrate, and the second PTS layer may be at a second depth below the second channel that is greater than the first depth. Furthermore, the first channel may include a first superlattice, and the second channel may include a second superlattice.

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[#9899479] - Semiconductor Devices with Superlattice Layers Providing Halo Implant Peak Confinement and Related Methods
PATENT NUMBER: 9899479 
PUBLICATION DATE: 11/17/2016

Abstract:

A semiconductor device may include a semiconductor substrate, and a plurality of field effect transistors (FETs) on the semiconductor substrate. Each FET may include a gate, spaced apart source and drain regions on opposite sides of the gate, upper and lower vertically stacked superlattice layers and a bulk semiconductor layer therebetween between the source and drain regions, and a halo implant having a peak concentration vertically confined in the bulk semiconductor layer between the upper and lower superlattices.

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[#10840388] - Varactor With Hyper-Abrupt Junction Region Including A Superlattice
PATENT NUMBER: 10840388 
PUBLICATION DATE: 11/17/2020

Abstract:

A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate. The hyper-abrupt junction region may include a first semiconductor layer having a first conductivity type, a superlattice layer on the first semiconductor layer, and a second semiconductor layer on the superlattice layer and having a second conductivity type different than the first conductivity type. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first contact coupled to the hyper-abrupt junction region, and a second contact coupled to the substrate to define a varactor.

See Patent

[#10825902] - Varactor With Hyper-Abrupt Junction Region Including Spaced-Apart Superlattices
PATENT NUMBER: 10825902 
PUBLICATION DATE: n/a

Abstract:

A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate. The hyper-abrupt junction region may include a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and a second superlattice layer on the second semiconductor layer. The semiconductor device may further include a first contact coupled to the hyper-abrupt junction regions and a second contact coupled to the substrate to define a varactor. The first and second superlattices may each include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

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[#9972685] - Vertical Semiconductor Devices Including Superlattice Punch Through Stop Layer and Related Methods
PATENT NUMBER: 9972685 
PUBLICATION DATE: 4/7/2016

Abstract:

A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.

See Patent

[#9275996] - Vertical Semiconductor Devices Including Superlattice Punch Through Stop Layer and Related Methods
PATENT NUMBER: 9275996 
PUBLICATION DATE: 5/28/2015

Abstract:

A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.

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[#6141361] - Wavelength Selective Filter
PATENT NUMBER: 6141361 
PUBLICATION DATE: n/a

Abstract:

A tunable optical wavelength selective filter is constituted by a dynamic holographic diffraction element (3) in combination with a fixed diffraction grating or hologram (2). The dynamic diffraction element (3) is preferably implemented as an electronically controlled image displayed on a pixelated spatial light modulator and in particular a spatial light modulating using photo-electronic integrated circuits fabricated using silicon VLSI technology and integrated with ferro-electric liquid crystals. Amongst other uses the filter can be implemented to form a digitally tunable laser.

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