In planar CMOS devices, a vertical well profile is typically engineered by one or more implants, which then broaden under diffusion processes during subsequent oxidations and other thermal processing steps. In more advanced planar devices, there is also a “halo” or “pocket” implant, which is performed after the gate, to boost the well doping and reduce off-state leakage. Since most of the leakage occurs below the very narrow surface region which is inverted in the on- state, and where on-state conduction occurs, it is preferable to have low surface doping but higher doping underneath. This is where the MST® magic comes to the fore. Whereas gate oxidation processes, halo implants and subsequent anneals tend to “smear out” the doping; MST can facilitate “precision doping profiles” which are “frozen in place” and do not smear out after oxidations, halo implants and anneals. It does this by blocking some of the common diffusion mechanisms.
In two recent papers, first presented at the IEEE EDTM conference in 2018 [https://ieeexplore.ieee.org/document/8421512] and then invited in expanded form for the IEEE Journal of Electron Devices [https://ieeexplore.ieee.org/document/8476180], the Atomera team describes how the enhanced diffusion that takes place normally under oxidation processes, is inhibited by MST. The ability to “freeze” an implanted doping profile is an important engineering tool, which is also shown to be much more effective than previous schemes to inhibit diffusion by growing modified versions of silicon, such as silicon-germanium- carbon, and is widely applicable to regular silicon processes. The understanding behind the MST mechanism has also facilitated the building of a TCAD (transistor computer aided design) model for the MST process on the very widely used Synopsys (NASDAQ: SNPS) Sentaurus TM design suite of tools.