Mears Silicon Technology (MST®) supports analog circuit designers by providing additional features that are currently not available in a typical designer’s toolbox. Integrating MST into a process technology node, with a given lithography capability, enhances key transistor characteristics to enable low power designs, reduce variability, and allow for incremental reduction of chip size. For example, independent third party studies on PMIC chips estimate significant chip size reduction potential by utilizing MST.
MST’s transconductance (Gm) enhancement and variability reduction both enable low power designs. An additional benefit of MST technology is the reduction or even elimination of Halo Implant, a doping technique that is a critical source of 1/f noise. MST’s benefits to 1/f noise would improve the capability of any noise constrained chip design.
In addition, third-party studies on NLDMOS products estimated that On-Resistance (RDS or Ron) can be reduced significantly depending on the operating voltage. The same expert team estimates that Mixed-Signal/RF devices can achieve die size reduction, improved analog performance, and lower power.
MST designers can extend the life of process geometries by retrofitting their existing nodes with MST to improve performance, or by building the technology into new designs at future nodes to enhance the analog shrink rate.