This paper, with co-authors from UC Berkeley and Axcelis provides an experimental demonstration of an application of MST® to improve shallow junction technology. The data and associated simulations indicate that MST® is beneficial for achieving shallower junctions with lower sheet resistance for advanced scaled devices.

This paper with co-authors from Prof. Suman Datta’s group at Penn State University (now at University of Notre Dame) describes the experimental engineering and modeling of boron and phosphorus doping profiles with MST®. Applications in advanced planar and FinFET devices are discussed, in particular a novel FinFET punch-through stop design.

This paper with co-authors from UT Dallas and elsewhere describes the simulation of 28nm planar SRAM incorporating MST®. Significant improvements in SRAM yield and Vmin are demonstrated, which are expected to be important for ultra-low power applications.

This paper was invited for a special issue of the IEEE Journal of Electron Device Society based on the high ranking of the EDTM paper of the same title. It is an expanded version of the EDTM paper and includes new material on the TCAD modeling of boron and phosphorus dopants. The paper was written with an additional co-author from Synopsys, which is supporting MST® TCAD.

Comparison of SOI versus Bulk FinFET Technologies for 6T-SRAM Voltage Scaling at the 7-/8-nm Node

IEEE Transactions on Electron Devices, Vol. 64, Issue 1 January, 2017

This paper, with co-authors from UC Berkeley compares the implementation of MST® technology on bulk and SOI FinFETs. It shows that a bulk MST® FinFET provides almost all the benefits of the more challenging SOI implementation for the 7/8nm Node.

Extension of Planar Bulk n-Channel MOSFET Scaling With Oxygen Insertion Technology

IEEE Transactions Electron Devices, vol. 61, no. 9, pp 3345-3349, September 2014 September, 2014

Paper with co-authors from UC Berkeley describing the wide range of power and performance benefits of MST® to extend the industry scaling of low power bulk nMOS devices.

Electron mobility enhancement in (100) oxygen-inserted silicon channel

Applied Physics Letters 107, 123502 (2015) September, 2015

Applied Physics Letter with co-authors from SK Hynix and UC Berkeley detailing the origins of the very large (88%) measured increase in conductance (gm) for Oxygen Inserted (MST®) nMOS devices.

Oxygen-Inserted SegFET: A Candidate for 10 nm Node System-on-Chip Applications

2014 IEEE Silicon Nanoelectronics Workshop June 8, 2014

Paper with authors from UC Berkeley describing how MST® can enhance a new quasi-planar device, the SegFET, with performance that competes with the best 10nm generation devices for Systems-on-a-chip (SOC) applications.

Comparative Study of Uniform Versus Supersteep Retrograde MOSFET Channel Doping and Implications for 6T SRAM Yield

IEEE Transactions Electron Devices, vol. 60, no. 5, pp 1790-1793, May 2013 May 5, 2013

Joint paper with UC Berkeley simulating the improved yield and reduced minimum operating voltage of MST®-enabled 6-T SRAM cells with potentially up to 50% power savings.

Details the benefits of MST® for silicon and germanium p-type planar & FinFET devices over a wide range of technologies.

We demonstrate simultaneous nMOS and pMOS high-field mobility enhancement and variability reduction by inserting partial monolayers of oxygen during silicon epitaxy of the channel layer.

IEDM paper with UC Berkeley, introducing and calibrating the model for the MST® confinement effect using Synopsys Sentaurus platform simulation tools. Mobility (conductivity) enhancement for both nMOS and pMOS devices is demonstrated and predicted to be more effective than strain at the 14nm node.

Tunneling through superlattices: the effect of anisotropy and kinematic coupling

Journal of Physics: Condensed Matter, Volume 24, Number 49 November 12, 2012

Paper analyzing the origins of tunneling of carriers in various superlattice systems and providing a theoretical background for the observed reduction in gate leakage in MST® devices. Gate leakage is one of the sources of power loss and scaling limitation in advanced CMOS technology.

Silicon Superlattice on SOI for High Mobility and Reduced Leakage

IEEE International SOI Conference 2007 October 1-4, 2007

This joint experimental paper with authors from Texas Instruments and Sematech (ATDF) demonstrates the first MST® mobility enhancement and gate leakage reduction results for a MST-enhanced silicon-on-insulator (SOI) technology.