Atomera has demonstrated, with a support team of third party SRAM experts, the performance benefits of MST for SRAM devices by using Monte Carlo simulations to evaluate 6T-SRAM performance in both MST and non-MST process flows. SRAM yield results, without the use of circuit assist, show significant supply voltage (VDD) reduction capability enabled exclusively through MST’s parametric improvements.
SRAM models, created by the same SRAM design experts, indicate a significant up to 20% yield improvement for MST over baseline SRAM. In addition, VDD can be reduced by >150 mV at the same yield as achieved with baseline technology. MST’s performance benefits represent a significant improvement for low-power System on Chip (SoC) applications using embedded SRAM. Coupled with MST’s proven SRAM logic benefits including reduced read/write time, lower leakage current and improved static noise margin, these additional SRAM performance benefits are expected to deliver more than a full node of performance improvement, at a lower cost than moving to the next process geometry.