Logic and Processors

Logic circuit designers who make use of Mears Silicon Technology (MST) can expect to gain between a half to a full node of incremental transistor performance enhancement from their existing manufacturing process technology. With support of third party experts in SPICE modeling and logic sub-circuit simulations, Atomera created CMOS SPICE models for MST by translating standard 28nm foundry models into a 28nm MST SPICE model. The MST model is based on electrical parametric data from test chips run under wafer fab process conditions.

Sub-circuit simulations have been run using the standard foundry SPICE model compared to the MST model to estimate MST product enhancements on logic circuits. MST circuits demonstrated a boost in logic switching speeds up to 20 percent while reducing leakage currents by 10-15%. SRAM performance is also improved by MST, with read/write times cut by 20 to 30%, leakage currents lowered by 10-15% and improved static noise margin.

Gate Oxide reliability improvements already observed under Time Dependent Dielectric Breakdown (TDDB) testing are expected to enable a gate overdrive option that would result in even faster switching speeds (>30%) with leakage levels close to baseline.