FinFET Technology

New multi-gate or tri-gate structures, also known as Fin Field Effect Transistors (FinFETs), have been adopted for the high-volume production of CMOS integrated circuits beginning at the 22nm technology generation. These structures are superior in terms of electrostatic integrity and scaling, but present significant challenges in circuit design, manufacturing process and technology cost. One of the cost challenges is the selection of substrate wafers. Silicon-on-insulator (SOI) substrates would be ideal for the manufacture of FinFETs with low OFF state leakage, but they are considered significantly more expensive compared to conventional bulk-Si wafers. Commercially implemented high performance FinFET technology using bulk silicon substrates (Bulk FinFETs) require heavy punch-through stopper (PTS) doping at the base of the fin to suppress OFF-state leakage current. A conventional doping process results in a dopant gradient within the fin (channel region) which degrades transistor ON-state current. In addition, heavy doping results in process-induced variation in transistor performance, which poses serious challenges for achieving high yields in large static RAM (SRAM) arrays.

Oxygen insertion technology or MST in Bulk FinFETs allows the creation of a super-steep retrograde profile at the base of the fin that optimizes PTS doping and reduces random dopant fluctuation to enhance ON and OFF state transistor performance. 

With optimized MST punch through stopper and source/drain doping profiles, an improvement of 21% in IDLIN and 10% in IDSAT over a 22 nm process technology baseline is expected. Additionally, MST® reduces random dopant fluctuation and is expected to improve fluctuation in gate threshold voltage (Sigma VT). This data is based on third party simulation analysis by experts in FinFET technology. The improvements on a 22nm technology node represent a performance enhancement of almost an entire technology node.