Mears Silicon Technology (MST®) allows DRAM designers to reduce chip size without moving to a new technology node, enabling product enhancements and cost reductions within a current design or for new designs. This capability is particularly effective for staying ahead of the market-driven DRAM learning curve, or the typical average sales price (ASP) erosion over time. With MST in place, new design features are available that allow designers to optimize supply voltage (VDD) to reduce both active and standby power for mobile products and for power-hungry applications such as server farms.

Insertion of MST in next generation chip designs enables circuit designers to reduce supply voltage (VDD) even further and optimize read/write conditions to modern LPDDR 5 requirements. Third party DRAM product design experts estimate that MST represents up to one node of incremental performance improvement over a given process technology .

Other MST advantages for DRAM include improvements in on-state/off-state current ratio (Ieff/Ioff) and mismatch improvement (sense-amplifier enhancements). MST technology provides an additional degree of freedom to optimize low voltage and high performance memory products.